Page 5 - Spec Tech Vol 1 Issue 04
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NASA Awards Next-Generation Spaceflight
Computing Processor Contract
NASA’s Jet Propulsion Laboratory in will significantly improve the overall computing
Southern California has selected Microchip efficiency for these missions by enabling
Technology Inc. of Chandler, Arizona, to computing power to be scalable, based on
develop a High-Performance Spaceflight mission needs. The design also will be more
Computing (HPSC) processor that will reliable and have a higher fault tolerance. The
provide at least 100 times the computational processor will enable spacecraft computers to
capacity of current spaceflight computers. perform calculations up to 100 times faster than
This key capability would advance all types today’s state-of-the-art space computers. As part
of future space missions, from planetary of NASA's ongoing commercial partnership
exploration to lunar and Mars surface efforts, the work will take place under a $50
missions. million firm-fixed-price contract, with Microchip
contributing significant research and
“This cutting-edge spaceflight processor will development costs to complete the project.
have a tremendous impact on our future
space missions and even technologies here
on Earth,” said Niki Werkheiser. “This effort Place on Moon
will amplify existing spacecraft capabilities
and enable new ones and could ultimately be Copernicus crater:
used by virtually every future space mission, Visible as the bright
all benefiting from more capable flight spot amidst the dark
computing.” maria, Copernicus, at
Microchip will architect, design, and deliver 107 km in diameter,
the HPSC processor over three years, with offers the greatest
the goal of employing the processor on visual contrast of any
future lunar and planetary exploration lunar crater to human
missions. Microchip’s processor architecture eyes.
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